This relates to a fractional-N type frequency synthesizer.
Frequency synthesizers generate an output signal having a frequency that is a multiple of a reference frequency. In a typical prior art circuit shown in FIG. 1 which is reproduced from FIG. 1 of U.S. Pat. No. 3,217,267, the operation of the frequency synthesizer is controlled by a phase lock loop (PLL) in which a variable frequency oscillator 2 is locked to the frequency of a known reference frequency 8 by a phase discriminator 6. In such arrangement, the oscillator typically is a voltage controlled oscillator (VCO) and the phase discriminator generates an output voltage that is proportional to the phase difference between the known reference frequency and the output of the oscillator. The output voltage of the phase discriminator is applied as an error signal to control the output frequency of the VCO.
To provide for different output frequencies from the VCO, a variable frequency divisor 4 is used to divide the output frequency before it is compared with the reference frequency. As a result, the output frequency from the VCO is an exact multiple of the reference frequency; and, if the divisor is an integer, the smallest increment in the VCO output frequency is equal to the reference frequency. Thus, to provide a small step size between adjacent output frequencies when using an integer divisor, a very low reference frequency is required. A low reference frequency, however, introduces a variety of unacceptable effects.
To avoid the use of a low reference frequency, circuits have been devised for dividing the output frequency by a fractional number. The prior art circuit shown in FIG. 2 which is FIG. 1 of U.S. Pat. No. 5,038,117, comprises a voltage controlled oscillator 11, a fractional divider 13, a phase comparator 15 and a filter 17. A control circuit 18 controls the integer component N and the fractional component .F by which the output frequency is divided. As is known in the art, different techniques may be used to effect fractional N division. In one such technique, division by N.F is achieved by averaging the divisor such that the output frequency is divided by N for .F of a duty cycle and by N+1 for (1xe2x88x92.F) of the duty cycle.
Further details concerning such fractional-N frequency synthesizers may be found in U.S. Pat. Nos. 3,217,267 and 5,038,117, which are incorporated herein by reference.
Unfortunately, switching between divisors results in an undesirable phase error or phase jitter near the carrier frequency. Techniques for reducing such phase error are also known and are described in U.S. Pat. No. 4,609,881 and in Steven R. Norsworthy et al. (Ed.) Delta-Sigma Data Converters Theory, Design, and Simulation, IEEE Press (1997), which are incorporated herein by reference, as well as in the above-referenced U.S. Pat. Nos. 3,217,267 and 5,038,117. As shown in FIG. 3 which is reproduced from FIG. 3.3 of Delta-Sigma Data Converters, a general technique for reducing such phase error is to cascade multiple stages of first or second order Delta-Sigma modulators 310, 320, 330 and supply an output of each stage to digital cancellation logic 340. The general form of each modular stage is shown in FIG. 4 which is adapted from FIG. 3.1 of Delta-Sigma Data Converters. As shown in FIG. 4, the modulator comprises first and second summers 412, 413, first and second filters 415, 419 and a quantizer 417. Filter 419 connects an output signal, y(n), from quantizer 417 to a negative input of first summer 412 which combines an input signal x(n) with the filtered output and provides the result to an input to filter 415. An output of filter 415 is provided to an input to quantizer 417. Second summer 413 calculates the difference between the signals at the input and the output of quantizer 417 to generate a signal, e(n), representing the quantization error of the quantizer. Ideally, for the circuit of FIG. 3 the noise transfer function is (1xe2x88x92Zxe2x88x921)m, where m is the overall order. Such a function has m coincident zeroes at z=1 in the Z-transform plane.
A model of the Delta-Sigma modulator of FIG. 3 is shown in FIG. 5 which is reproduced from FIG. 5(d) of the ""117 patent. Here, each of three identical stages 510, 520, 530 comprises first and second summers 512, 513, an integrator 515, a quantizer 517 and a Zxe2x88x921 delay 519. A digital cancellation logic circuit 540 comprises a first differentiator 542 coupled to the output of the second stage 520, second and third differentiators 544, 546 coupled in cascade to the output of the third stage 530 and summer circuitry 550 coupled to the outputs of the first stage 510, the first differentiator 542 and the third differentiator 546. A series of error terms arising at different stages of the circuit of FIG. 5 are canceled when the terms are combined. In particular, following equation 16 of the ""117 patent, the combined output of the circuit of FIG. 5 can be written
O=f+(1xe2x88x92Zxe2x88x921)Q1xe2x88x92(1xe2x88x92Zxe2x88x921)Q1+(1xe2x88x92Zxe2x88x921)2 Q2xe2x88x92(1xe2x88x92Zxe2x88x921)2 Q2+(1xe2x88x92Zxe2x88x921)3 Q3
where Qn is the quantization error associated with stage n. This equation reduces to
O=f+(1xe2x88x92Zxe2x88x921)3 Q3.
As will be recognized by those skilled in the art, this equation has three coincident zeroes at z=1 in the Z-transform plane.
An actual implementation of the Delta-Sigma modulator of FIG. 5 is shown in FIG. 6.
Here, each of three identical stages 610, 620, 630 comprise an adder 614 and a Zxe2x88x921 delay 619. A digital cancellation logic circuit 640 comprises a first differentiator 642, coupled to the carry output of adder 614 of the second stage 620, second and third differentiators 644, 646 coupled in cascade to the carry output of adder 614 of the third stage 630 and summer circuitry coupled to the carry output of the adder 614 of the first stage 610, the output of the first differentiator 642 and the output of the third differentiator 646.
While prior art circuits of the type shown in FIGS. 3, 5 and 6 have better performance than conventional fractional-N synthesizer circuits, there is still a need for even better performance.
We have devised such a circuit. With reference to the Z-transform plane, such better performance is achieved by separating the zeroes in the Z-transform plane. As a result, the spectrum of the noise components of the fractional-N divisor is shifted away from the carrier frequency, thereby reducing the components near the carrier frequency and increasing the components farther away. This is advantageous because it is possible to remove the higher frequency components from the divisor signal by conventional filtering techniques. The model of a circuit for separating the zeroes is similar to that of FIG. 4 and comprises a first summer, first and second filters and a quantizer. The second filter connects an output of the quantizer to the first summer and an output of the summer is connected to an input of the first filter and an output of the first filter is connected to an input to the quantizer. In accordance with the invention, the second filter introduces off-axis zeroes into equations representative of this circuit. In a preferred embodiment, the second filter is realized by first and second delay elements connected in cascade, a multiplier and a second summer. An input to the first delay element is connected to the output of the quantizer and an output of the second delay element is connected to an input to the second summer. An input to the multiplier is connected to a node between the first and second delay elements and an output of the multiplier is connected to an input to the second summer. The second summer subtracts the signal from the second delay element from the signal from the multiplier and provides it as an input to the first summer.
The invention may also be implemented in software to generate fractional N divisors having desirable spectral characteristics.